Distributed shared memory (DSM) multiprocessor systems are typically designed with either a special interconnect for input/output traffic or a special bridge that connects input/output modules directly or indirectly to the primary interconnect of the system. Input/output modules may be integrated into each node of the system and thus may use the node structures to ultimately reach the system interconnect when necessary.
The result is that the input/output configuration in conventional DSM systems is typically very limited and inflexible. Designs based on a special input/output traffic interconnect suffer from redundant resources (one interconnect for input/output and one for data), which may be underutilized. Designs based on special bridges typically treat each input/output module as subordinate to a processor, and so the number of input/output modules can not be increased without a corresponding, costly increase in the number of processors.
It would be desirable to have a multi-node multiprocessor computer system that is more flexible with respect to input/output configurations, preferably allowing the number of input/output modules to be increased or decreased without regard to the number of processors in the system, while also unifying the data and input/output interconnects.
It would furthermore be desirable to have a multiprocessor system in which input/output modules and processors are treated as being participants in the general system interconnect and in the cache coherency mechanism. In such a system there would be no need for a special input/output interconnect or bridge, because the input/output modules would communicate data requests and data modifications to the rest of the system via the normal protocol of the cache coherence mechanism. Such a system would furthermore be capable of being configured with an arbitrary ratio of input/output modules and processors.